The next limit on AI chips lies past the transistor in the package that holds everything together, and TSMC has named its answer. The company is preparing CoPoS, or chip-on-panel-on-substrate, a packaging method that swaps the round silicon wafer for a large rectangular panel, with mass production set for the second half of 2028. The analyst Ming-Chi Kuo expects Nvidia's Feynman accelerator, the chip after Rubin, to be the first major product built on it. The shift matters because packaging, once an afterthought, now decides how big and how cheap an AI chip can be.
From round wafers to square panels
The change is geometric at heart. Today's advanced packaging, CoWoS (chip-on-wafer-on-substrate), builds AI chips on a round 300mm silicon wafer, which wastes space at the curved edges and caps how large a single package can grow. CoPoS moves the work onto a large rectangular panel TSMC has shown a 310mm by 310mm format which uses the area far better and supports chip surfaces several times the size of a standard lithography field. Kuo also corrected a common misread about the glass: CoPoS uses it as a temporary carrier during assembly, then as a core layer in the final substrate between films of Ajinomoto Build-up Film, with the chips bonded to that film. The result drops the silicon interposer that sits at the heart of CoWoS.
| CoWoS (current) | CoPoS (2028) | |
|---|---|---|
| Format | Round 300mm wafer | Rectangular panel (~310×310mm) |
| Interposer | Silicon interposer | Glass-core substrate with ABF, no silicon interposer |
| Package size | Near current reticle limits | Ultra-large, above 9. 5x reticle |
| Main gain | Proven, in volume | Less edge waste, larger packages, lower cost per die |
| First major chip | Nvidia Blackwell and Rubin | Nvidia Feynman |
| Status | In mass production | Mass production 2H 2028 |
Why CoWoS ran out of room
The push comes from a hard ceiling. As AI chips grow, their packages outrun what a round wafer can carry: Nvidia's Rubin GPU already spans about 5.5 times the reticle the largest area a lithography tool can print in one pass and a 300mm wafer now yields as few as four to seven of the biggest dies.
CoPoS is built for the packages beyond that, with Kuo placing its target above the 9.5-times-reticle class. The panel format also trims the edge waste of round wafers, so TSMC can package more dies per run and lower the cost of each the rare advance that promises both larger chips and cheaper ones.
Feynman goes first
Nvidia sits at the front of the queue. Its Feynman architecture, the successor to Rubin and due around 2028, is expected to need package sizes past the practical limit of CoWoS, which makes it the natural first home for CoPoS.
More panel area lets Nvidia pack additional compute dies, high-bandwidth memory stacks and networking silicon into one package, the recipe its largest AI accelerators rely on. The timing lines up: CoPoS reaches volume as Feynman arrives.
TSMC versus Intel's EMIB-T
TSMC has company in this race. Intel is pushing its own large-package method, EMIB-T, and reports suggest Nvidia is testing Intel's packaging for Feynman as a hedge a notable opening, given TSMC's near-monopoly on high-end AI packaging and the strain on its CoWoS capacity. Samsung is working on panel-level packaging too.
The contest marks a shift in where chip leadership is decided: for decades it turned on the transistor and the process node, and now it turns as much on how the pieces are joined.
A pilot line, then 2028
The runway is already visible. TSMC's CoPoS pilot line began receiving tools in February and was set for completion around mid-2026, with a mini line at its VisEra unit this year, small trial runs in 2027, and volume production between 2028 and 2029.
That cadence puts the first commercial CoPoS chips two years out, which leaves time for the design and yield problems any new packaging method brings, glass handling among them.
India's bet sits in packaging
For India, the relevance is direct and awkward at once. The country's semiconductor plan leans on packaging and assembly rather than leading-edge fabs, with Micron's Sanand plant in Gujarat and Tata Electronics' site in Assam anchoring the push. That places India in the same broad layer of the chain that CoPoS belongs to. The gap, though, is wide: India's first plants handle conventional assembly and test, while CoPoS sits at the frontier of advanced packaging for Nvidia-class AI chips.
The opportunity is real but long-dated the lesson of CoPoS is that packaging now carries strategic weight, and India has chosen the right layer to build in, even as the frontier stays several steps ahead.
FAQ
What is TSMC CoPoS?
CoPoS, short for chip-on-panel-on-substrate, is TSMC's next packaging method. It builds AI chips on a large rectangular panel rather than a round wafer, to support bigger packages at lower cost.
How is CoPoS different from CoWoS?
CoWoS uses a round silicon wafer with a silicon interposer. CoPoS uses a rectangular panel with a glass-core substrate and ABF layers, removing the silicon interposer and allowing larger chips.
When will CoPoS enter mass production?
In the second half of 2028, with a volume ramp running into 2029, according to Ming-Chi Kuo and TrendForce.
Which chip uses CoPoS first?
Nvidia's Feynman AI accelerator, the successor to Rubin, is expected to be the first major product built on CoPoS.
Does CoPoS use a glass interposer?
No. Kuo clarified that glass acts as a temporary carrier and as a core in the final substrate between ABF layers, with chips bonded to the ABF rather than to a glass interposer.
Why does advanced packaging matter for AI?
As transistor scaling slows, packaging decides how many compute dies and memory stacks fit in one chip. It now shapes both the performance and the cost of AI accelerators.
What does CoPoS mean for India?
India's semiconductor push centres on packaging and assembly, so the global shift toward advanced packaging is strategically relevant — though CoPoS-class work sits well ahead of India's current conventional plants.